The invention relates generally to automatic test equipment for testing semiconductor devices, and more particularly a pattern generator for use in a memory tester to test burst or packed-based memory devices.
Random Access Memory (RAM) comprises the largest segment of the semiconductor memory market. Of the numerous kinds of RAM memories, one of the more dominant memory types is Dynamic RAM (DRAM). The high performance and low cost characteristics of DRAM make it suitable for mass applications in PC and workstation main memories.
In an effort to improve the data rates to and from DRAM memories, memory manufacturers have devised ways of accessing groups of cells in the memory core in bursts, or packets. These memories, such as Rambus Direct DRAM (DRDRAM), are often referred to as burst or packet-based memories. The memory structure generally includes a plurality of input/output (I/O) pins that double as both inputs and outputs for the device. Each I/O pin receives and sends respective packet signals of predetermined burst lengths to and from the device.
The packets generally comprise respective serial-bit waveforms that contain address bits specifying locations in the memory for storing data bits. Each packet includes a single packet address that identifies a device-under-test (DUT) column and row location for initially accessing a group of cells from the memory core. A plurality of data bits in the packet are then read from or written to the core with respect to the single packet address according to a DUT mapping methodology.
In conventional memory testers for conventional 1-bit wide memory devices, data generators in the tester generate data bits for application to the DUT according to the address information. Conventional data generators typically have single-bit outputs and require as inputs a cell address that designates where the data is to be applied in the DUT. An algorithmic pattern generator generally specifies the row and column location, or address, for each data bit and feeds the address information to the data generator. The data bits are then written to the specified addresses in the DUT core and subsequently read from the DUT and compared to expected data values to determine whether any failures occurred.
For conventional memory devices having 1-bit widths, data patterns are written to the device in a straightforward manner based on the row and column address of the physical memory array. Moreover, the serial bit rate of the address and data bits typically correspond to the operating frequency of the DUT.
However, at the present time, most DRAMS are 16-bits wide. Rambus Direct DRAM is an 18-bit wide part with a burst length of 8 words. This generally means that the internal memory array of the DUT is accessed 144 bits at a time (8*18=144).
In order to accurately test the internal cells of the memory core, the writing and reading of the data from and to the DUT must be done in a predictable and repetitive manner. Thus, the individual data bits for each packet must have respective addresses corresponding to a specific cell in the core in order for the tester to successfully track the actual versus expected data values from the DUT.
One possible solution to testing packet-based memories involves implementing an address generator that matches the DUT frequency. With RAM devices expected to exceed the 1 GigaHertz threshold, such an address generator would be difficult to implement. Further, unless one of the generated addresses for data generation corresponds to the address the user desires to apply to the address pins of the DUT, the tester would have to generate an additional address.
An alternative solution to the single high-speed address generator proposed above is to provide a plurality of slower pattern generators in parallel, each having respective address generators. A proposal similar to this solution is disclosed in U.S. Pat. No. 5,796,748 to Housako et ai. To test a memory having an operating frequency M with a pattern generator of a frequency L, N pattern generators are used in parallel according to the relationship M=Nxc3x97L.
Although the multiple-pattern generator solution is allegedly easier to implement due to the individually slower speeds, it requires N times the amount of hardware. This is highly undesirable when attempting to minimize the number of gates on integrated circuits, and the size of the circuits. Moreover, like the single high-speed address generator approach, unless one of the data bit""s addresses can be used for the DUT, the tester must, for example, generate a 9th address.
An additional problem with both approaches above involves the relative difficulty for the user in programming software to keep all the data bit addresses in sync as they are applied to the DUT. As an example, for a given address associated with bit xe2x80x9c0xe2x80x9d, there is only one legal address for bits xe2x80x9c1xe2x80x9d through xe2x80x9cNxe2x80x9d. It could be a fairly monumental task to debug such programmed patterns.
What is needed and heretofore unavailable is a memory tester that offers a minimal hardware solution to the address problem described above in testing packet-based memory devices. Moreover, the need exists for such a memory tester to have such capability with little modification to conventional memory tester constructions. Further, the need exists for testing packet-based memory devices while providing maximum operating convenience for a user. The packet-based memory tester of the present invention satisfies these needs.
The packet-based memory tester of the present invention provides a unique pattern generator that offers a minimal hardware-based solution to identifying the internal addresses of a DUT that are associated with a DUT packet address. The solution provides this capability with minimal modifications to existing hardware designs and maximizes the operating convenience of the tester for a user.
To realize the foregoing advantages, the invention in one form comprises a pattern generator for use in a memory tester to provide packet address and data signals to a packet-based memory-under-test. The pattern generator includes an address source for generating an external packet memory address signal. The external packet memory address signal represents a plurality of addressable memory elements in the memory-under-test. A plurality of data generators are disposed in parallel relationship and coupled to the output of the address source to receive at least a portion of the packet memory address signal. Each of the data generators have logic operative to derive an internal address from the packet address. Each internal address corresponds to an individual memory element within the memory under test. A sequencer is disposed at the outputs of the data generators to distribute the data generator outputs in a packet waveform for application to the memory-under-test.
In another form, the invention comprises a semiconductor memory tester including a user workstation and a tester body responsive to the user workstation. The tester body includes control logic for generating test commands, and a pattern generator for generating packet address and data signals for application to the memory-under-test. The pattern generator includes an address source and a plurality of data generators coupled in parallel to the address source. The data generators have logic to receive a portion of the packet address signal and operative to derive respective internal addresses of the memory-under-test from the packet address. The pattern generator further includes a sequencer to distribute the data generator outputs into a packet waveform. Conditioning circuitry is disposed at the output of the sequencer in the tester body to format the waveform. A test head couples to the tester body and includes interface circuitry adapted to couple to the memory-under-test to drive signals to and compare signals from the memory-under-test.
In yet another form, the invention comprises a data generator for use in a pattern generator adapted to test packet-based memory devices. The data generator includes a row address input for receiving a packet row address, a column address input for receiving a packet column address, and logic having an input for receiving the packet column address. The logic is operative to derive a plurality of internal addresses from the packet address.
In yet another form, the invention comprises a burst address control circuit for use in a pattern generator adapted to test packet-based memory devices. The burst address control circuit includes a seed address selector for identifying a seed address, a counter, and a burst address look-up table for remapping predetermined internal addresses in the packet column address for signal interleaving. The burst address lookup table is responsive to the seed address and the counter value to identify the burst sequence of the internal addresses.
Other features and advantages of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.